This application is related to copending and concurrently filed application Ser. No. 270,951 entitled DYNAMICALLY ASSIGNABLE I/O STORAGE CONTROLLER CACHE.
This invention is related to data processing devices, and more particularly to data processing devices including a host processor and a plurality of attachment devices in a storage heirarchy.
In data processing systems, it is common to have one or more attachment devices, e.g., storage disks, for storage and retrieval of information. For example, in U.S. Pat. No. 4,038,642 to Bouknecht et al issued on July 26, 1977 and assigned to the same assignee as the present application, a plurality of I/O devices and associated I/O controllers are commonly connected to a host processor via an I/O interface bus. Each of the I/O attachment devices includes a microprocessor which cooperates with the host processor to implement data transfer between the main storage and the I/O device. An improvement on the Bouknecht et al system is described in U.S. Pat. No. 4,246,637 to Brown et al where a single I/O controller including a microprocessor is coupled to the host processor, and the plurality of data storage attachment devices are coupled to the output of the I/O controller so that a single microprocessor can coordinate data transfers to and from a plurality of attachment devices.
A problem in each of these systems is that each time the host processor requires data from one of the attachment device, it must access the appropriate attachment device, and this can be a time consuming procedure. For example, in Brown et al, when data is to be transferred to the host processor from an appropriate attachment disk under Direct Program Control (DPC), command and data words are transferred from the main storage of the host processor to the microprocessor, and thence to a device data register. The appropriate coordination and control logic is exercised to retrieve the requested data from the appropriate attachment disk and to provide them to the host processor. For the reverse operation, i.e., writing into a disk from the main storage, the data to be written into the attachment storage device is loaded into the device data register and then the appropriate handshaking routines must be carried out to transfer this data into the desired attachment disk. In a Cycle Steal mode of operation, commands are provided to the micrprocessor which enable it to "steal" data from the host processor main storage and load this data into the device data register, and the data is then transferred to the appropriate attachment disk in substantially the same manner as in the DPC mode.
Even though the speed of the system is improved, it is still necessary that one of the desired attachment disks be accessed in order to obtain the necessary information for the host processor. While signal processing speeds are quite fast, the time required to access an attachment storage device is limited by the necessity of physically moving the read/write heads or the storage medium, e.g. processing speeds are limited in disk subsystems by the time required for the disk to be rotated and for the head to seek the proper position.
In order to achieve improvements in operating speed, it is know to utilize a low capacity high-speed memory to store a portion of the main storage data which is most likely to be needed by the central processing unit so that many of the data requests of the cpu can be satisfied rather quickly from this small high-speed memory. Such a technique is disclosed, for example, in U.S. Pat. No. 4,035,778 issued on July 12, 1977 to Ghanem and assigned to the same assignee as the present application. Ghanem '778 discusses the use of low capacity high-speed working memories and the need to maximize the efficiency of such memories by constantly updating the memory contents to keep the data which is most likely to be needed in the near future. This could be done via a Least Recently Used (LRU) technique wherein the least recently used data is constantly being replaced, or could be done through the more complex technique of Ghanem wherein a complicated statistical algorithm is used to allocate memory capacity among multiple users. Ghanem '778, however, is directed to the allocation of working memory space among competitive programs, but there is no suggestion of utilizing a similar technique in a multiple disk I/O controller. Further, in order to determine if requested data is presently stored in the high-speed working memory, it is necessary to compare the data request identification with the entire contents of the working memory, which may be a time consuming operation. Still further, the only data transferred to the working memory is the data requested by the CPU, and efficiency could further be improved by transferring some additional data which has not yet been requested but is nevertheless likely to be required in the near future.